Project case study
RV32I Instruction Set Emulator
A lightweight RISC-V emulator in C with a fetch-decode-execute pipeline, simulated memory, and hand-assembled instruction tests for validating core CPU behavior.
Architecture focus
This project was a good forcing function for understanding CPU behavior at a level where every register update and bitwise operation has to make sense.
I built the emulator around a simple RV32I instruction subset with 1 KB of simulated memory and 32 registers.
How I validated it
Instead of hiding behind tooling, I wrote and tested against hand-assembled machine code so the ALU and execution flow could be checked directly.
